Motorola MCF5281 사용자 설명서
MOTOROLA
Chapter 23. UART Modules
23-19
Operation
• The system clock supplies an asynchronous clock source that is divided by 32 and
then divided by the 16-bit value programmed in UBG1n and UBG2n. See
Section 23.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).”
Section 23.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).”
The choice of DTIN or system clock is programmed in the UCSR.
Figure 23-18. Clocking Source Diagram
NOTE
If DTINn is a clocking source for either the timer or UART, that
timer module cannot use DTINn for timer capture.
timer module cannot use DTINn for timer capture.
23.5.1.2 Calculating Baud Rates
The following sections describe how to calculate baud rates.
23.5.1.2.1 System Clock Baud Rates
When the system clock is the UART clocking source, it goes through a divide-by-32
prescaler and then passes through the 16-bit divider of the concatenated UBG1n and
UBG2n registers. The baud-rate calculation is as follows:
prescaler and then passes through the 16-bit divider of the concatenated UBG1n and
UBG2n registers. The baud-rate calculation is as follows:
Using a 66MHz system clock and letting baud rate = 9600, then
UART
On-Chip
DTIN
x1
Prescaler
x16
Prescaler
Clock
Generator
16-Bit
Divider
x32
Prescaler
DTIN
Clocking sources programmed in UCSR
Timer Module
DTOUTn
DTINn
UTXDn
URXDn
Tx
Rx
Rx Buffer
Tx Buffer
System
Clock
16-Bit
Divider
16-Bit
Divider
Baudrate
SYSCLK
32 x divider
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