Motorola MCF5281 사용자 설명서

23-22

MOTOROLA

 

The receiver is enabled through its UCRn, as described in Section 23.3.5, “UART
Command Registers (UCRn).”

When the receiver detects a high-to-low (mark-to-space) transition of the start bit on
URXD, the state of URXD is sampled eight times on the edge of the bit time clock starting
one-half clock after the transition (asynchronous operation) or at the next rising edge of the
bit time clock (synchronous operation). If URXD is sampled high, the start bit is invalid
and the search for the valid start bit begins again. 

If URXD is still low, a valid start bit is assumed and the receiver continues sampling the
input at one-bit time intervals, at the theoretical center of the bit, until the proper number
of data bits and parity, if any, is assembled and one stop bit is detected. Data on the URXD
input is sampled on the rising edge of the programmed clock source. The lsb is received
first. The data is then transferred to a receiver holding register and USRn[RxRDY] is set.
If the character is less than eight bits, the most significant unused bits in the receiver
holding register are cleared.

C1

1

C2

C3

Break

C4

C6

UTXDn

Transmitter

Enabled

USRn[TxRDY]

W

2

W

W

W

W

W

W

W

UCTSn

3

URTSn

4

Manually asserted 

by 

BIT

-

SET

 command

Manually 

asserted

Start

break

C5

not

transmitted

C6

C4 Stop

break

C3

C2

C1

1

C1 in transmission

3 

UMR2n[TxCTS] = 1

1 

Cn = transmit characters

2 

W = write

4 

UMR2n[TxRTS] = 1

internal

module

select