Motorola MCF5281 사용자 설명서

MOTOROLA

C Interface  

24-3

The I

2

C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer.

For I

2

C compliance, all devices connected to these two signals must have open drain or

open collector outputs. The logic AND function is exercised on both lines with external
pull-up resistors.

Out of reset, the I

2

C default state is as a slave receiver. Thus, when not programmed to be

a master or responding to a slave transmit address, the I

2

C module should return to the

The I

2

C module is designed to be compatible with the Philips

I

2

C bus protocol. For information on system configuration,

protocol, and restrictions, see The I

Version 2.1.

Normally, a standard communication is composed of the following parts: 

1. START signal—When no other device is bus master (both SCL and SDA lines are 

at logic high), a device can initiate communication by sending a START signal (see 
A in Figure 24-2). A START signal is defined as a high-to-low transition of SDA 
while SCL is high. This signal denotes the beginning of a data transfer (each data 
transfer can be several bytes long) and awakens all slaves.

2. Slave address transmission—The master sends the slave address in the first byte 

after the START signal (B). After the seven-bit calling address, it sends the R/W bit 
(C), which tells the slave data transfer direction. 
Each slave must have a unique address. An I

2

C master must not transmit its own 

slave address; it cannot be master and slave at the same time. 

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9 9

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

XXX

D7 D6 D5

D4 D3

D2 D1

D0

Calling Address

R/W ACK

Bit

Data Byte

No

ACK

Bit

STOP

Signal

lsb

msb

lsb

msb

SDA

SCL

START

Signal

A

B

D

C

E

F

SCL held low while
Interrupt is serviced

Interrupt bit set
(Byte complete)