Motorola MCF5281 사용자 설명서

24-10

MOTOROLA

 

In master-receive mode, reading the I2DR, shown in Figure 24-9, allows a read to occur
and initiates next byte data receiving. In slave mode, the same function is available once
the I

2

C has received its slave address.

The following examples show programming for initialization, signaling START,
post-transfer software response, signalling STOP, and generating a repeated START. 

Before the interface can transfer serial data, registers must be initialized, as follows:

1. Set I2FDR[IC] to obtain SCL frequency from the system bus clock. See 

2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I

2

C bus interface system.

4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, 

and interrupt-enable or not.

1

IIF

I

2

C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine. 

0 No I

2

C interrupt pending

1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the 

following occurs:

 • Complete one byte transfer (set at the falling edge of the ninth clock)
 • Reception of a calling address that matches its own specific address in slave-receive mode
 • Arbitration lost

0

RXAK Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle. 

0  An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1  No acknowledge signal was detected at the ninth clock.

7

6

5

4

3

2

1

0

Field

Data

Reset

0000_0000

R/W

R/W

Address

IPSBAR + 0x310