Motorola MCF5281 사용자 설명서
29-20
MCF5282 User’s Manual
MOTOROLA
Background Debug Mode (BDM)
29.5.3 BDM Command Set
Table 29-17 summarizes the BDM command set. Subsequent paragraphs contain detailed
descriptions of each command. Issuing a BDM command when the processor is accessing
debug module registers using the WDEBUG instruction causes undefined behavior.
descriptions of each command. Issuing a BDM command when the processor is accessing
debug module registers using the WDEBUG instruction causes undefined behavior.
Unassigned command opcodes are reserved by Motorola. All unused command formats
within any revision level perform a
within any revision level perform a
NOP
and return the illegal command response.
Table 29-17. BDM Command Summary
Command
Mnemonic
Description
CPU
State
1
1
General command effect and/or requirements on CPU operation:
- Halted. The CPU must be halted to perform this command.
- Steal. Command generates bus cycles that can be interleaved with bus accesses.
- Parallel. Command is executed in parallel with CPU activity.
- Halted. The CPU must be halted to perform this command.
- Steal. Command generates bus cycles that can be interleaved with bus accesses.
- Parallel. Command is executed in parallel with CPU activity.
Section
Command
(Hex)
Read A/D
register
register
RAREG
/
RDREG
Read the selected address or data register and return the
results through the serial interface.
results through the serial interface.
Halted
0x218 {A/D,
Reg[2:0]}
Reg[2:0]}
Write A/D
register
register
WAREG
/
WDREG
Write the data operand to the specified address or data
register.
register.
Halted
0x208 {A/D,
Reg[2:0]}
Reg[2:0]}
Read memory
location
location
READ
Read the data at the memory location specified by the
longword address.
longword address.
Steal
0x1900—byte
0x1940—word
0x1980—lword
0x1940—word
0x1980—lword
Write memory
location
location
WRITE
Write the operand data to the memory location specified
by the longword address.
by the longword address.
Steal
0x1800—byte
0x1840—word
0x1880—lword
0x1840—word
0x1880—lword
Dump
memory block
memory block
DUMP
Used with
READ
to dump large blocks of memory. An
initial
READ
is executed to set up the starting address of
the block and to retrieve the first result. A
DUMP
command retrieves subsequent operands.
Steal
0x1D00—byte
0x1D40—word
0x1D80—lword
0x1D40—word
0x1D80—lword
Fill memory
block
block
FILL
Used with
WRITE
to fill large blocks of memory. An
initial
WRITE
is executed to set up the starting address of
the block and to supply the first operand. A
FILL
command writes subsequent operands.
Steal
0x1C00—byte
0x1C40—word
0x1C80—lword
0x1C40—word
0x1C80—lword
Resume
execution
execution
GO
The pipeline is flushed and refilled before resuming
instruction execution at the current PC.
instruction execution at the current PC.
Halted
0x0C00
No operation
NOP
Perform no operation; may be used as a null command.
Parallel
0x0000
Read control
register
register
RCREG
Read the system control register.
Halted
0x2980
Write control
register
register
WCREG
Write the operand data to the system control register.
Halted
29.5.3.3.10 0x2880
Read debug
module
register
module
register
RDMREG
Read the debug module register.
Parallel
29.5.3.3.11 0x2D {0x4
2
DRc[4:0]}
2
0x4 is a three-bit field.
Write debug
module
register
module
register
WDMREG
Write the operand data to the debug module register.
Parallel
29.5.3.3.12 0x2C {0x4
DRc[4:0]}