Motorola MCF5281 사용자 설명서
1-14
MCF5282 User’s Manual
MOTOROLA
MCF5282 Key Features
1.1.14 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The
watchdog counter is a free-running down-counter that generates a reset on underflow. To
prevent a reset, software must periodically restart the countdown.
watchdog counter is a free-running down-counter that generates a reset on underflow. To
prevent a reset, software must periodically restart the countdown.
1.1.15 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced
frequency divider (RFD), status/control registers, and control logic. To improve noise
immunity, the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL.
All other circuits are powered by the normal supply pins, VDD and VSS.
frequency divider (RFD), status/control registers, and control logic. To improve noise
immunity, the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL.
All other circuits are powered by the normal supply pins, VDD and VSS.
1.1.16 DMA Controller
The Direct Memory Access (DMA) controller module provides an efficient way to move
blocks of data with minimal processor interaction. The DMA module provides four
channels (DMA0–DMA3) that allow byte, word, longword or 16-byte burst line transfers.
These transfers are triggered by software, explicitly setting a DCRn[START] bit or the
occurrence of a hardware event from one of the on-chip peripheral devices, such as a
capture event or an output reference event in a DMA timer (DTIMn) for each channel. The
DMA controller supports dual-address mode to on-chip devices.
blocks of data with minimal processor interaction. The DMA module provides four
channels (DMA0–DMA3) that allow byte, word, longword or 16-byte burst line transfers.
These transfers are triggered by software, explicitly setting a DCRn[START] bit or the
occurrence of a hardware event from one of the on-chip peripheral devices, such as a
capture event or an output reference event in a DMA timer (DTIMn) for each channel. The
DMA controller supports dual-address mode to on-chip devices.
1.1.17 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset
signals to the system, and keep track of what caused the last reset. The power management
registers for the internal low-voltage detect (LVD) circuit are implemented in the reset
module. There are seven sources of reset:
signals to the system, and keep track of what caused the last reset. The power management
registers for the internal low-voltage detect (LVD) circuit are implemented in the reset
module. There are seven sources of reset:
• External
• Power-on reset (POR)
• Watchdog timer
• Phase-locked loop (PLL) loss of lock
• PLL loss of clock
• Software
• Low-voltage detection (LVD) reset
• Power-on reset (POR)
• Watchdog timer
• Phase-locked loop (PLL) loss of lock
• PLL loss of clock
• Software
• Low-voltage detection (LVD) reset
External reset on the RSTO pin is software-assertable independent of chip reset state. There
are also software-readable status flags indicating the cause of the last reset, and LVD
control and status bits for setup and use of LVD reset or interrupt.
are also software-readable status flags indicating the cause of the last reset, and LVD
control and status bits for setup and use of LVD reset or interrupt.