Motorola MCF5281 사용자 설명서

29-44

MOTOROLA

 

The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. The PST/DDATA specification for these opcodes is shown in
Table 29-24.

The move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value,
indicating an entry into user mode. Additionally, if the execution of a RTE instruction
returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled.

Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted
state (PST = 0xF) display this status throughout the entire time the ColdFire processor is in
the given mode.

move.l

Accy,Rx

PST = 0x1

move.l

MACSR,CCR PST = 0x1

move.l

MACSR,Rx

PST = 0x1

move.l

MASK,Rx PST = 0x1 

move.l

Accext01,Rx

PST = 0x1

move.l

Accext23,Rx

PST = 0x1

msac.l

Ry,Rx,Accx

PST = 0x1

msac.l

Ry,Rx,<ea>,Rw,Accx

PST = 0x1, {PST = 0xB, DD = source operand}

msac.w

Ry,Rx,Accx

PST = 0x1

msac.w

Ry,Rx,<ea>,Rw,Accx

PST = 0x1, {PST = 0xB, DD = source operand}

cpushl

PST = 0x1

halt

PST = 0x1, 
PST = 0xF

move.w

SR,Dx

PST = 0x1

move.w

{Dy,#imm},SR

PST = 0x1, {PST = 0x3}

movec

Ry,Rc

PST = 0x1

rte

PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB, 
DD =source operand}, 
PST = 0x5, {[PST = 0x9AB], DD = target address}

stldsr.w

#imm

PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}

stop

#imm

PST = 0x1, 
PST = 0xE

wdebug

<ea>y

PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}