Motorola MCF5281 사용자 설명서

MOTOROLA

Chapter 30.  Chip Configuration Module (CCM)  

30-5

The following subsection describes the CCM registers.

15

14

11

10

8

7

6

5

4

3

2

0

Field LOAD

—

MODE

—

SZEN PSTEN

—

BME

BMT

Reset

See Note

R/W

R/W

Read Only

R/W

Address

IPSBAR + 0x11_0004

Note:  The reset value of the LOAD and MODE fields is determined during reset configuration. The SZEN is set for 
master mode and cleared for all other configurations. The BME bit is set to enable the bus monitor and all other bits in 
the register are cleared at reset.

15

LOAD

Pad driver load. The LOAD bit selects full or partial drive strength for selected pad output drivers. For 

maximum capacitive load, set the LOAD bit to select full drive strength. For reduced power consumption 
and reduced electromagnetic interference (EMI), clear the LOAD bit to select partial drive strength.

0 Default drive strength.
1 Full drive strength.
Table 30-2 shows the read/write accessibility of this write-once bit.

14–11

—

Reserved, should be cleared.

10–8

MODE

Chip configuration mode. This read-only field reflects the chip configuration mode.
000-101 Reserved.
110  Single-chip mode.
111  Master mode.

7

—

Reserved, should be cleared.

6

SZEN

SIZ[1:0] enable. This read/write bit enables the SIZ[1:0] function of the external pins.
0 SIZ[1:0] function disabled.
1 SIZ[1:0] function enabled.

5

PSTEN

PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data 

(DDATA)n functions of the external pins.

0 PST/DDATA function disabled.
1 PST/DDATA function enabled.

4

—

Reserved, should be cleared.