Motorola MCF5281 사용자 설명서
33-16
MCF5282 User’s Manual
MOTOROLA
Processor Bus Output Timing Specifications
Figure 33-5. SDRAM Read Cycle
Table 33-12. SDRAM Timing
NUM
Characteristic
1
1
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
Symbol
Min
Max
Unit
D1
CLKOUT high to SDRAM address valid
t
CHDAV
—
10
ns
D2
CLKOUT high to SDRAM control valid
t
CHDCV
—
10
ns
D3
CLKOUT high to SDRAM address invalid
t
CHDAI
2
—
ns
D4
CLKOUT high to SDRAM control invalid
t
CHDCI
2
—
ns
D5
SDRAM data valid to CLKOUT high
t
DDVCH
6
—
ns
D6
CLKOUT high to SDRAM data invalid
t
CHDDI
1
—
ns
D7
2
2
D7 and D8 are for write cycles only.
CLKOUT high to SDRAM data valid
t
CHDDVW
—
10
ns
D8
2
CLKOUT high to SDRAM data invalid
t
CHDDIW
2
—
ns
A[23:0]
SRAS
D[31:0]
ACTV
NOP
SDRAM_CS[1:0]
READ
Column
CLKOUT
0
DRAMW
BS[3:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
D1
D2
D4
D6
D5
D4
1
DACR[CASL] = 2
SCAS
1
NOP
D4
Row
D3
PRE