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Motorola
MC68VZ328
사용자 설명서
Motorola MC68VZ328 사용자 설명서
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376
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List of Tables
xix
Table 1-1
Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table 1-2
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Table 2-1
Signal Function Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Table 3-1
Programmer’s Memory Map (Sorted by Address) . . . . . . . . . . . . . . . . . . . . . . . 3-2
Table 3-2
Programmer’s Memory Map (Sorted by Register Name) . . . . . . . . . . . . . . . . . 3-8
Table 4-1
CGM Clock Signal Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2
PLL Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-3
WKSEL Field (PLLCR) Delay Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4-4
PLL Frequency Select Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Table 4-5
Power Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Table 5-1
System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Table 5-2
Peripheral Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Table 5-3
ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Table 5-4
I/O Drive Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Table 6-1
Chip-Select and Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Table 6-2
Chip-Select Group A Base Address Register Description . . . . . . . . . . . . . . . . . 6-4
Table 6-3
Chip-Select Group B Base Address Register Description . . . . . . . . . . . . . . . . . 6-5
Table 6-4
Chip-Select Group C Base Address Register Description . . . . . . . . . . . . . . . . . 6-5
Table 6-5
Chip-Select Group D Base Address Register Description . . . . . . . . . . . . . . . . . 6-6
Table 6-6
Chip-Select Upper Group Base Address Register Description . . . . . . . . . . . . . 6-6
Table 6-7
Chip-Select Register A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Table 6-8
Chip-Select Register B Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Table 6-9
Chip-Select Register C Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Table 6-10
Chip-Select Register D Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Table 6-11
Emulation Chip-Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Table 6-12
Chip-Select Control Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Table 6-13
Chip-Select Control Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Table 6-14
Chip-Select Control Register 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Table 7-1
DRAM Address Multiplexing Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Table 7-2
16 Mbit SDRAM—256 (16-Bit) and 512 (8-Bit) Page Size . . . . . . . . . . . . . . . 7-5
Table 7-3
64 Mbit SDRAM—256 (16-Bit) and 512 (8-Bit) Page Size . . . . . . . . . . . . . . . 7-5
Table 7-4
128 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page Size . . . . . . . . . . . . . 7-6
Table 7-5
256 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page Size . . . . . . . . . . . . . 7-6
Table 7-6
DRAM Memory Configuration Register Description . . . . . . . . . . . . . . . . . . . 7-12
List of Tables
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