Motorola MC68VZ328 사용자 설명서
LCD Controller Signals
Signal Descriptions
2-7
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IRQ5/PF1—Interrupt Request 5 or Port F bit 1. This signal can be programmed as GPIO or as an
interrupt input. When configured as an interrupt input, the signal may be programmed as a level high
or level low trigger interrupt. This pin defaults to GPIO input pulled high.
interrupt input. When configured as an interrupt input, the signal may be programmed as a level high
or level low trigger interrupt. This pin defaults to GPIO input pulled high.
•
EMIQ—Emulator Interrupt Status
.
This bit indicates that the in-circuit emulation module or
EMUIRQ pin is requesting a level 7 interrupt. This bit can be generated from three interrupt
sources—two breakpoint interrupts from the in-circuit emulation module and an external interrupt
from EMUIRQ, which is an active low, edge-sensitive interrupt. To clear this interrupt, read the
ICEMSR register to identify the interrupt source and write a 1 to the corresponding bit in the
ICEMSR. See Section 9.6.4, “Interrupt Status Register,” on page 9-12 for more information.
sources—two breakpoint interrupts from the in-circuit emulation module and an external interrupt
from EMUIRQ, which is an active low, edge-sensitive interrupt. To clear this interrupt, read the
ICEMSR register to identify the interrupt source and write a 1 to the corresponding bit in the
ICEMSR. See Section 9.6.4, “Interrupt Status Register,” on page 9-12 for more information.
2.8
LCD Controller Signals
The MC68VZ328 contains all necessary circuitry to support an external LCD display panel. This section
describes the signals used by the LCD controller. It also provides some programming information about
the use of these signals.
describes the signals used by the LCD controller. It also provides some programming information about
the use of these signals.
•
LD[3:0]/PC[3:0], LD[7:4]/PK[7:4]—LCD Data Bus bits 7–0, or Port C bits 3–0 and Port K bits
7–4. LD signals output bus transfers of pixel data to the LCD panel to which it will be displayed.
The pixel data is arranged to accommodate the programmable panel mode data width selection.
Panel interfaces of 1, 2, 4, or 8 bits are supported.
7–4. LD signals output bus transfers of pixel data to the LCD panel to which it will be displayed.
The pixel data is arranged to accommodate the programmable panel mode data width selection.
Panel interfaces of 1, 2, 4, or 8 bits are supported.
NOTE:
The MC68VZ328’s LCD interface data bus uses the LSB (LD0) to display
pixel 0,0. Some LCD panel manufacturers program their LCD panel data
bus so that the MSB of the panel displays pixel 0,0. For these panels, the
connection between the MC68VZ328’s LCD data bus and the LCD panel’s
data bus may have a reversed bit significance. For a 4-bit LCD panel of this
type, connect the MC68VZ328’s LD0 signal to the LCD panel’s data bit 3,
and then connect LD1 to LCD data 2, LD2 to LCD data 1, and LD3 to LCD
data 0. The four pins can also be programmed as I/O ports from Port C.
These signals default as GPIO input with Port C being pulled low and Port
K pulled high.
pixel 0,0. Some LCD panel manufacturers program their LCD panel data
bus so that the MSB of the panel displays pixel 0,0. For these panels, the
connection between the MC68VZ328’s LCD data bus and the LCD panel’s
data bus may have a reversed bit significance. For a 4-bit LCD panel of this
type, connect the MC68VZ328’s LD0 signal to the LCD panel’s data bit 3,
and then connect LD1 to LCD data 2, LD2 to LCD data 1, and LD3 to LCD
data 0. The four pins can also be programmed as I/O ports from Port C.
These signals default as GPIO input with Port C being pulled low and Port
K pulled high.
•
LFLM/PC4—First Line Marker or Port C bit 4. This signal indicates the start of a new display
frame. LFLM becomes active after the first line pulse of the frame and remains active until the next
line pulse, at which point it deasserts and remains inactive until the next frame. LFLM can be
programmed to be an active high or an active low signal. It can also be programmed as an I/O port.
This pin defaults to GPIO input pulled low.
frame. LFLM becomes active after the first line pulse of the frame and remains active until the next
line pulse, at which point it deasserts and remains inactive until the next frame. LFLM can be
programmed to be an active high or an active low signal. It can also be programmed as an I/O port.
This pin defaults to GPIO input pulled low.
•
LLP/PC5—LCD Line Pulse or Port C bit 5. The LLP signal is used to latch a line of shifted data
onto an LCD panel. The LLP can be programmed to be an active high or active low signal in
software. See Section 8.3.10, “LCD Polarity Configuration Register,” on page 8-16 for more
information.
onto an LCD panel. The LLP can be programmed to be an active high or active low signal in
software. See Section 8.3.10, “LCD Polarity Configuration Register,” on page 8-16 for more
information.
•
LCLK/PC6—LCD Shift Clock or Port C bit 6. This is the clock output to which the output data to
the LCD panel is synchronized. LCLK can be programmed to be either an active high or an active
low signal. This pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled
low.
the LCD panel is synchronized. LCLK can be programmed to be either an active high or an active
low signal. This pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled
low.
•
LACD/PC7—LCD Alternate Crystal Direction or Port C bit 7. This output is toggled to alternate
the crystal polarization on the panel. This signal can be programmed to toggle at a period of 1 to
128 frames or lines. This pin also can also be programmed as an I/O port. This pin defaults to GPIO
input pulled low.
the crystal polarization on the panel. This signal can be programmed to toggle at a period of 1 to
128 frames or lines. This pin also can also be programmed as an I/O port. This pin defaults to GPIO
input pulled low.