Motorola MC68VZ328 사용자 설명서
6-8
MC68VZ328 User’s Manual
Programming Model
6.3.3
Chip-Select Registers
There are four 16-bit chip-select (CSA, CSB, CSC, and CSD) registers for each corresponding chip-select
base address register. Each register controls two chip-select signals and can be configured to select the
memory type and size of the memory range supported as well as to program the required wait states or use
the external DTACK signal. The settings for the registers are described in Table 6-7 through Table 6-10 on
page 6-14.
base address register. Each register controls two chip-select signals and can be configured to select the
memory type and size of the memory range supported as well as to program the required wait states or use
the external DTACK signal. The settings for the registers are described in Table 6-7 through Table 6-10 on
page 6-14.
CSA
Chip-Select Register A
0x(FF)FFF110
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
RO
FLASH
BSW
WS3–1
SIZ
EN
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
RESET
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0x00B0
Table 6-7. Chip-Select Register A Description
Name Description
Setting
RO
Bit 15
Bit 15
Read-Only—This bit sets the chip-select to
read-only. Otherwise, read and write accesses
are allowed. A write to a read-only area will
generate a bus error if the BETEN bit of the
SCR is set. See Section 5.2.1, “System Control
Register,” on page 5-2 for more information.
read-only. Otherwise, read and write accesses
are allowed. A write to a read-only area will
generate a bus error if the BETEN bit of the
SCR is set. See Section 5.2.1, “System Control
Register,” on page 5-2 for more information.
0 = Read/write.
1 = Read-only.
1 = Read-only.
Reserved
Bits 14–9
Bits 14–9
Reserved
These bits are reserved and should be set to 0.
FLASH
Bit 8
Bit 8
Flash Memory Support—When enabled, this
bit provides support for flash memory by forc-
ing the LWE/UWE signal to go active after
chip-select.
bit provides support for flash memory by forc-
ing the LWE/UWE signal to go active after
chip-select.
Note:
This bit is used for expanded memory
size for CSD when the DRAM bit in the CSD
register is enabled.
register is enabled.
0 = The chip-select and LWE/UWE signals go active
at the same clock edge.
1 = The chip-select signal goes low 1 clock before
LWE/UWE.
BSW
Bit 7
Bit 7
Data Bus Width—This bit sets the data bus
width for this chip-select area.
width for this chip-select area.
0 = 8 bit.
1 = 16 bit.
1 = 16 bit.
WS3–1
Bits 6–4
Bits 6–4
Wait State—This field determines the number
of wait states added before an internal DTACK
signal is returned for this chip-select.
of wait states added before an internal DTACK
signal is returned for this chip-select.
Note:
When using the external DTACK
signal, you must configure the
BUSW/DTACK/PG0 pin.
BUSW/DTACK/PG0 pin.
000 = 0 + WS0 wait states.
001 = 2 + WS0 wait states.
010 = 4 + WS0 wait states.
011 = 6 + WS0 wait states.
100 = 8 + WS0 wait states.
101 = 10 + WS0 wait states.
110 = 12 + WS0 wait states.
111 = External DTACK.
001 = 2 + WS0 wait states.
010 = 4 + WS0 wait states.
011 = 6 + WS0 wait states.
100 = 8 + WS0 wait states.
101 = 10 + WS0 wait states.
110 = 12 + WS0 wait states.
111 = External DTACK.
When using the external DTACK signal, you must
select DTACK function in Port G.
select DTACK function in Port G.
WS0 is the DWS0, CWS0, BWS0, or AWS0 bit in
the CSCTRL1 register.
the CSCTRL1 register.