Panasonic MN103001G/F01K 사용자 설명서

Bus Controller (BC)

8-38

An

Dn

WEn

RE

CSn

EA

MCLK

SYSCLK

EA

 Read 

 Write 

BCE

BCE

REN

WEN

: Undefined

Fig. 8-13-9

Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data

Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

“Description of Registers.”

Fig. 8-13-8

Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data

Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”

An

Dn

WEn

RE

CSn

EA

MCLK

SYSCLK

EA

 Read 

 Write 

BCE

BCE

REN

WEN

: Undefined