Panasonic MN103001G/F01K 사용자 설명서
Interrupt Controller
9-7
Non-maskable interrupt control register
Register symbol: G0ICR (NMICR)
Address:
Address:
x'34000100
Purpose:
This register determines whether a non-maskable interrupt has been generated.
Bit No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
-
-
-
-
-
-
-
-
-
-
-
-
-
SYSE WDIF NMIF
name
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
Bit No.
Bit name
Description
0
NMIF
External non-maskable interrupt request flag
0: No interrupt request
1: Interrupt detected
1
WDIF
Watchdog timer overflow interrupt request flag
0: No interrupt request
1: Interrupt detected
2
SYSEF
System error interrupt request flag
0: No interrupt request
1: Interrupt detected
The method of clearing flag differs according to the interrupt request flags.
1. External non-maskable interrupt request flag (NMIF) and Watchdog timer overflow interrupt request flag (WDIF)
1. External non-maskable interrupt request flag (NMIF) and Watchdog timer overflow interrupt request flag (WDIF)
After a non-maskable interrupt is accepted, these flags can be cleared by writing to the non-maskable interrupt
control register (NMICR).
When a flag is set to “1”, write a “1” to the flag to clear it.
control register (NMICR).
When a flag is set to “1”, write a “1” to the flag to clear it.
The relationship between the flag status, the data written to the flag, and the new flag status after the data is
written is shown in the table below.
written is shown in the table below.
Flag status
Write data
Flag status after write
Flag change
0
0
0
No change.
0
1
0
No change.
1
0
1
No change.
1
1
0
Flag is cleared.
SYSEF
Note: A non-maskable interrupt cannot be generated through software.
2. System error interrupt request flag (SYSEF)
2. System error interrupt request flag (SYSEF)
This flag cannot be cleared by writing to the non-maskable interrupt control register (NMICR).
_______
This flag can be cleared by generating a reset interrupt by setting the RST pin to "L" level or by the self-reset,
which is generated by writing to the reset control register (RSTCTR) of the watchdog timer.
which is generated by writing to the reset control register (RSTCTR) of the watchdog timer.
Note*:
Normally, the serial debugger uses non-maskable interrupts. The following points should be observed when
performing user application processing using non-maskable interrupts, and when using the serial debugger:
• The non-maskable interrupt processing program should be written so that interrupt factors are checked
within the non-maskable interrupt processing program, and control branches to the debugger program for
all factors other than those that should be processed.
• The program should be written so that if the stack pointer (SP) is changed before branching to the debugger
program, control should branch after the stack pointer is set to the value when the interrupt was accepted.
*For details, refer to the“ MN1030 Series C Source Code Debugger User's Manual”.