Intel 820E 사용자 설명서

Intel

Intel

®

820E Chipset

R

Design Guide

5

LAN Layout Guidelines................................................................................................ 102

ICH2 – LAN Interconnect Guidelines ........................................................ 103

Bus Topologies............................................................................. 104

Point-to-Point Interconnect ........................................................... 104

LOM/CNR Interconnect ................................................................ 104

Signal Routing and Layout............................................................ 105

Crosstalk Consideration ............................................................... 106

Impedances .................................................................................. 106

Line Termination........................................................................... 106

General LAN Routing Guidelines and Considerations .............................. 107

General Trace Routing Considerations ........................................ 107

Trace Geometry and Length....................................... 108

Signal Isolation ........................................................... 108

Power and Ground Connections .................................................. 108

General Power and Ground Plane Considerations .... 108

4-Layer Board Design................................................................... 110

82562EH Home/PNA* Guidelines ................................................... 112

Power and Ground Connections .................................................. 112

Guidelines for Intel

82562EH Component Placement ................ 112

Crystals and Oscillators ................................................................ 112

Phoneline HPNA Termination....................................................... 113

Critical Dimensions....................................................................... 114

Distance from Magnetics Module to Line RJ11.......... 114

2.22.3.5.2.

Distance from Intel

®

82562EH Component to

Magnetics Module ...................................................... 114

Distance from LPF to Phone RJ11............................. 115

82562ET / Intel

82562EM Component Guidelines......................... 115

2.22.4.1.

Guidelines for Intel

82562ET / Intel

82562EM Component

Placement .................................................................................... 115

Crystals and Oscillators ................................................................ 116

2.22.4.3.

Intel

82562ET / Intel

82562EM Component Termination

Resistors .................................................................................... 116

Critical Dimensions....................................................................... 116

Distance from Magnetics Module to RJ45.................. 117

2.22.4.4.2.

Distance from the Intel

82562ET Component to the

Magnetics Module ...................................................... 118

Reducing Circuit Inductance......................................................... 118

Terminating Unused Connections ................................................ 118

Termination Plane Capacitance ................................. 118

82562ET/EM Disable Guidelines ....................................................... 119

2.22.6.

Intel

82562ET and Intel

82562EH Components’ Dual-Footprint

Guidelines.................................................................................................... 120

ICH2 Decoupling Recommendations ........................................................ 122

FWH Flash BIOS Guidelines....................................................................................... 124

In-Circuit FWH Flash BIOS Programming ................................................ 124

FWH Flash BIOS VPP Design Guidelines ................................................ 124

ICH2 Design Checklist ................................................................................................ 125

ICH2 Layout Checklist ................................................................................................. 134

Advanced System Bus Design................................................................................................. 139

Terminology and Definitions ........................................................................................ 139

AGTL+ Design Guidelines........................................................................................... 141

Initial Timing Analysis................................................................................ 142

Determine the Desired General Topology, Layout, and Routing............... 145