Texas Instruments TMS320DM643X DMP 사용자 설명서
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2.17 Power Management
2.18 Emulation Considerations
Peripheral Architecture
Each of the three main components of the EMAC peripheral can independently be placed in
reduced-power modes to conserve power during periods of low activity. The power management of the
EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a
master controller for power management on behalf of all of the peripherals on the device.
reduced-power modes to conserve power during periods of low activity. The power management of the
EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a
master controller for power management on behalf of all of the peripherals on the device.
The power conservation modes available for each of the three components of the EMAC/MDIO
peripheral are:
peripheral are:
•
Idle/Disabled state. This mode stops the clocks going to the peripheral, and prevents all the register
accesses. After reenabling the peripheral from this idle state, all the registers values prior to setting
into the disabled state are restored, and data transmission can proceed. No reinitialization is
required.
accesses. After reenabling the peripheral from this idle state, all the registers values prior to setting
into the disabled state are restored, and data transmission can proceed. No reinitialization is
required.
•
Synchronized reset. This state is similar to the Power-on Reset (POR) state, when the processor is
turned-on; reset to the peripheral is asserted, and clocks to the peripheral are gated after that. The
registers are reset to their default value. When powering-up after a synchronized reset, all the
EMAC submodules need to be reinitialized before any data transmission can happen.
turned-on; reset to the peripheral is asserted, and clocks to the peripheral are gated after that. The
registers are reset to their default value. When powering-up after a synchronized reset, all the
EMAC submodules need to be reinitialized before any data transmission can happen.
For more information on the use of the processor Power and Sleep Controller (PSC), see the
TMS320DM643x DMP DSP Subsystem Reference Guide (
TMS320DM643x DMP DSP Subsystem Reference Guide (
EMAC emulation control is implemented for compatibility with other peripherals. The SOFT and FREE
bits in the emulation control register (EMCONTROL) allow EMAC operation to be suspended.
bits in the emulation control register (EMCONTROL) allow EMAC operation to be suspended.
When the emulation suspend state is entered, the EMAC stops processing receive and transmit frames
at the next frame boundary. Any frame currently in reception or transmission is completed normally
without suspension. For transmission, any complete or partial frame in the transmit cell FIFO is
transmitted. For receive, frames that are detected by the EMAC after the suspend state is entered are
ignored. No statistics are kept for ignored frames.
at the next frame boundary. Any frame currently in reception or transmission is completed normally
without suspension. For transmission, any complete or partial frame in the transmit cell FIFO is
transmitted. For receive, frames that are detected by the EMAC after the suspend state is entered are
ignored. No statistics are kept for ignored frames.
shows how the SOFT and FREE bits affect the operation of the emulation suspend.
Note:
Emulation suspend has not been tested.
Table 6. Emulation Control
SOFT
FREE
Description
0
0
Normal operation
1
0
Emulation suspend
X
1
Normal operation
52
Ethernet Media Access Controller (EMAC)/
SPRU941A – April 2007
Management Data Input/Output (MDIO)