Texas Instruments TMS320DM643X DMP 사용자 설명서
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4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
MDIO Registers
The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
and described in
Figure 22. MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR)
31
16
Reserved
R-0
15
2
1
0
Reserved
USERINTMASKCLEAR
R-0
R/WC-0
LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear; -n = value after reset
Table 20. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
USERINTMASKCLEAR
MDIO user command complete interrupt mask clear for USERINTMASKED[1:0],
respectively. Setting a bit to 1 will disable further user command complete interrupts for
that particular USERACCESS register. USERINTMASKCLEAR[0] and
USERINTMASKCLEAR[1] correspond to USERACCESS0 and USERACCESS1,
respectively. Writing a 0 to this register has no effect.
respectively. Setting a bit to 1 will disable further user command complete interrupts for
that particular USERACCESS register. USERINTMASKCLEAR[0] and
USERINTMASKCLEAR[1] correspond to USERACCESS0 and USERACCESS1,
respectively. Writing a 0 to this register has no effect.
0
MDIO user command complete interrupts for the MDIO user access register n
(USERACCESSn) are enabled.
(USERACCESSn) are enabled.
1
MDIO user command complete interrupts for the MDIO user access register n
(USERACCESSn) are disabled.
(USERACCESSn) are disabled.
SPRU941A – April 2007
Ethernet Media Access Controller (EMAC)/
63
Management Data Input/Output (MDIO)