Texas Instruments TMS320DM643X DMP 사용자 설명서
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5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
Ethernet Media Access Controller (EMAC) Registers
The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in
and described in
Figure 36. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
TX7MASK
TX6MASK
TX5MASK
TX4MASK
TX3MASK
TX2MASK
TX1MASK
TX0MASK
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
R/WC-0
LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 35. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
TX7MASK
0-1
Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
6
TX6MASK
0-1
Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
5
TX5MASK
0-1
Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
4
TX4MASK
0-1
Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
3
TX3MASK
0-1
Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
2
TX2MASK
0-1
Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
1
TX1MASK
0-1
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0
TX0MASK
0-1
Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
78
Ethernet Media Access Controller (EMAC)/
SPRU941A – April 2007
Management Data Input/Output (MDIO)