Texas Instruments TMS320DM357 사용자 설명서
www.ti.com
53
Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
54
Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)
55
Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)
56
Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)
57
Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)
58
Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)
59
Receive CPPI Completion Pointer (RCPPICOMPPTR)
60
Function Address Register (FADDR)
61
Power Management Register (POWER)
62
Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX)
63
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
64
Interrupt Enable Register for INTRTX (INTRTXE)
65
Interrupt Enable Register for INTRRX (INTRRXE)
66
Interrupt Register for Common USB Interrupts (INTRUSB)
67
Interrupt Enable Register for INTRUSB (INTRUSBE)
68
Frame Number Register (FRAME)
69
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
70
Register to Enable the USB 2.0 Test Modes (TESTMODE)
71
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
72
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
73
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
74
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
75
Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
76
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
77
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
78
Control Status Register for Host Receive Endpoint (HOST_RXCSR)
79
Count 0 Register (COUNT0)
80
Receive Count Register (RXCOUNT)
81
Type Register (Host mode only) (HOST_TYPE0)
82
Transmit Type Register (Host mode only) (HOST_TXTYPE)
83
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)
84
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)
85
Receive Type Register (Host mode only) (HOST_RXTYPE)
86
Receive Interval Register (Host mode only) (HOST_RXINTERVAL)
87
Configuration Data Register (CONFIGDATA)
88
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
89
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
90
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
91
Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
92
Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
93
OTG Device Control Register (DEVCTL)
94
Transmit Endpoint FIFO Size (TXFIFOSZ)
95
Receive Endpoint FIFO Size (RXFIFOSZ)
96
Transmit Endpoint FIFO Address (TXFIFOADDR)
97
Receive Endpoint FIFO Address (RXFIFOADDR)
98
Transmit Function Address (TXFUNCADDR)
99
Transmit Hub Address (TXHUBADDR)
100
Transmit Hub Port (TXHUBPORT)
101
Receive Function Address (RXFUNCADDR)
102
Receive Hub Address (RXHUBADDR)
103
Receive Hub Port (RXHUBPORT)
SPRUGH3 – November 2008
List of Figures
7