Texas Instruments TMS320DM357 사용자 설명서
4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
Registers
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The Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) is shown in
and described
in
Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
31
16
Reserved
R-0
15
4
3
0
Reserved
COMP_PENDING_INTR_EN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved
3-0
COMP_PENDING_INTR_EN
0-Fh
Transmit CPPI High Priority Interrupt Enables
These are active high interrupt enables corresponding to the Transmit CPPI High
Priority Completion Pending status bits.
Priority Completion Pending status bits.
The Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) is shown in
and
described in
.
Figure 35. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
31
16
Reserved
R-0
15
4
3
0
Reserved
COMP_PENDING_INTR_EN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
0
Reserved
3-0
COMP_PENDING_INTR_EN
0-Fh
Writing a 1 to any of the bits in the Transmit CPPI Interrupt Enable Clear Register will
result in clearing of the corresponding bit in the Transmit CPPI High Priority Interrupt
Enable Register.
result in clearing of the corresponding bit in the Transmit CPPI High Priority Interrupt
Enable Register.
Universal Serial Bus (USB) Controller
96
SPRUGH3 – November 2008