National Instruments PC-LPM-16/PnP 사용자 설명서

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Chapter 3     Theory of Operation
 
 
 National Instruments Corporation
3-3
PC-LPM-16/PnP User Manual
 
PC I/O Channel Interface Circuitry
 
The PC I/O channel interface circuitry consists of an address bus, a data 
bus, interrupt lines, and several control and support signals. The 
components making up the PC-LPM-16PnP PC I/O channel interface 
circuitry are shown in Figure 3-2.
 
Figure 3-2.  
 
PC I/O Interface Circuitry Block Diagram
 
The circuitry consists of Plug and Play address decoders, data buffers, 
I/O channel interface timing control circuitry, and interrupt control 
circuitry. The circuitry monitors address lines SA4 through SA15 to 
generate the board enable signal, and uses lines SA0 through SA3 plus 
timing signals to generate the onboard register select signals and 
read/write signals. The data buffers control the direction of data transfer 
on the bidirectional data lines based on whether the transfer is a read or 
write operation.
The interrupt control circuitry routes any enabled interrupts to the 
selected interrupt request line. The PC-LPM-16PnP has six interrupt 
Address Bus
Control Lines
Data Bus
IRQ
Register Selects
Read & Write Signals
Internal Data Bus
Interrupt Requests
Plug and 
Play Circuitry
Timing
Interface
Data
Buffers
Plug and
Play Interrupt
Control
Address
Decoder
PC I/O Channel
 
a.Book : g.chapter 3  Page 3  Wednesday, November 20, 1996  6:36 PM