National Instruments DIO 6533 사용자 설명서

Chapter 5

Signal Timing

DIO 6533 User Manual

5-8

© National Instruments Corporation

Figure 5-7 shows the timing diagram for 8255 emulation mode.

Figure 5-7.  8255 Emulation Timing

t

r*r

REQ low duration

75

—

t

rr*

REQ high duration

75

—

t

a*r

ACK falling edge to REQ rising edge

0

—

t

dir

Input data valid to REQ rising edge

0

—

t

rdi

REQ rising edge to input data invalid

10

—

t

aa*

ACK high duration

100

—

t

r*a

REQ falling edge to ACK rising edge

—

150

t

doa*

Output data valid to ACK falling edge

25

—

t

rdo

REQ rising edge to output data invalid

100

—

All timing values are in nanoseconds.

REQ

ACK

Data Out

Data In

tdoa*

tdir

ta*r

tr*r

trr*

trdi

trdo

taa*

tr*a