National Instruments DIO 6533 사용자 설명서

Chapter 5

Signal Timing

© National Instruments Corporation

5-31

DIO 6533 User Manual

Figure 5-27.  Burst Mode Input Timing (Default)

t

rs

Setup time from REQ valid to PCLK

12

—

t

rh

Hold time from PCLK to REQ invalid

0

—

t

dis

Setup time from input data valid to PCLK

4

—

t

dih

Hold time from PCLK to input data invalid

6

—

t

pc

PCLK cycle time

50

700

1

t

pw

PCLK high pulse duration

t

pc

/2 – 5

t

pc

/2 + 5

t

pa

PCLK to ACK valid

—

18

t

ah

Hold time from PCLK to ACK invalid

3

—

1

 t

pc

 = programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase 

stability for the onboard 20 MHz clock source is 50 ppm. 

All timing values are in nanoseconds.

PCLK

ACK

Data In

REQ

tdis

tdih

trs

tpa

tpw

tpc

trh

tah