Epson MFJ-1278B 사용자 설명서
MFJ-1278B MULTI-MODE HARDWARE
Transistors Q5 and Q6 are used to isolate the battery from the +5 volt line when main power
is available. R33 protects the lithium battery from overload conditions and provides a
convenient means of monitoring battery current drain when the TNC is switched off. JMP5
provides a means of disconnecting the negative side of the lithium battery for MFJ-1278B
maintenance.
U2 and associated components form a charge-pump voltage inverter which generates an
unregulated negative supply for the RS-232C drivers.
U3c, Q2, CR6 and surrounding components provide a regulated source of -5 volts for the
modem chips.
The modem power sources and ground are isolated from digital logic switching noise by
inductor L2.
is available. R33 protects the lithium battery from overload conditions and provides a
convenient means of monitoring battery current drain when the TNC is switched off. JMP5
provides a means of disconnecting the negative side of the lithium battery for MFJ-1278B
maintenance.
U2 and associated components form a charge-pump voltage inverter which generates an
unregulated negative supply for the RS-232C drivers.
U3c, Q2, CR6 and surrounding components provide a regulated source of -5 volts for the
modem chips.
The modem power sources and ground are isolated from digital logic switching noise by
inductor L2.
RS-232C HANDSHAKING PROTOCOL
The CTS, DSR and DTR lines of the RS-232C port, J1, are used for hardware
"handshaking" protocol to control the flow of data between the terminal (DTE) and the
MFJ-1278B (DCE).
The MFJ-1278B always asserts Data Set Ready (DSR) on J1 pin 6 via resistor R16. Thus,
whenever the MFJ-1278B is powered up, it signals to the terminal connected to J1 that the
MFJ-1278B is "on line."
The terminal indicates it is ready to receive data from the MFJ-1278B by asserting its Data
Terminal Ready (DTR) output, J1 pin 20. The MFJ-1278B will send data when it has data to
send and DTR is asserted. If the terminal is not ready to receive data, it should negate (make
false) DTR to the MFJ- 1278B. Thus, data flow from the MFJ-1278B to the terminal is
controlled by the use of the DTR line. The state of the DTR line is ignored by the software if
"software flow control" is enabled in this direction.
The MFJ-1278B asserts its Clear To Send (CTS) output, J1 pin 5, whenever it is ready to
receive data from the terminal. If the MFJ-1278B's buffers fill, it will negate CTS, signaling
the terminal to stop sending data. The MFJ-1278B will assert CTS when it is again ready to
receive data from the terminal. Thus, data flow from the terminal to the MFJ-1278B is
controlled by the use of the CTS line. The CTS line is always asserted if "software flow
control" is enabled in this direction.
"handshaking" protocol to control the flow of data between the terminal (DTE) and the
MFJ-1278B (DCE).
The MFJ-1278B always asserts Data Set Ready (DSR) on J1 pin 6 via resistor R16. Thus,
whenever the MFJ-1278B is powered up, it signals to the terminal connected to J1 that the
MFJ-1278B is "on line."
The terminal indicates it is ready to receive data from the MFJ-1278B by asserting its Data
Terminal Ready (DTR) output, J1 pin 20. The MFJ-1278B will send data when it has data to
send and DTR is asserted. If the terminal is not ready to receive data, it should negate (make
false) DTR to the MFJ- 1278B. Thus, data flow from the MFJ-1278B to the terminal is
controlled by the use of the DTR line. The state of the DTR line is ignored by the software if
"software flow control" is enabled in this direction.
The MFJ-1278B asserts its Clear To Send (CTS) output, J1 pin 5, whenever it is ready to
receive data from the terminal. If the MFJ-1278B's buffers fill, it will negate CTS, signaling
the terminal to stop sending data. The MFJ-1278B will assert CTS when it is again ready to
receive data from the terminal. Thus, data flow from the terminal to the MFJ-1278B is
controlled by the use of the CTS line. The CTS line is always asserted if "software flow
control" is enabled in this direction.