Intel 8XC251SQ 사용자 설명서
6-5
INTERRUPT SYSTEM
6.3
PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT
The programmable counter array (PCA) interrupt is generated by the logical OR of five event
flags (CCFx) and the PCA timer overflow flag (CF) in the CCON register (see Figure 9-8 on page
9-14). All PCA interrupts share a common interrupt vector. Bits are not cleared by hardware vec-
tors to service routines. Normally, interrupt service routines resolve interrupt requests and clear
flag bits. This allows the user to define the relative priorities of the five PCA interrupts.
flags (CCFx) and the PCA timer overflow flag (CF) in the CCON register (see Figure 9-8 on page
9-14). All PCA interrupts share a common interrupt vector. Bits are not cleared by hardware vec-
tors to service routines. Normally, interrupt service routines resolve interrupt requests and clear
flag bits. This allows the user to define the relative priorities of the five PCA interrupts.
The PCA interrupt is enabled by bit EC in the IE0 register (see Figure 6-1). In addition, the CF
flag and each of the CCFx flags must also be individually enabled by bits ECF and ECCFx in reg-
isters CMOD and CCAPMx respectively for the flag to generate an interrupt (see Figure 9-8 on
page 9-14 and Figure 9-9 on page 9-15).
flag and each of the CCFx flags must also be individually enabled by bits ECF and ECCFx in reg-
isters CMOD and CCAPMx respectively for the flag to generate an interrupt (see Figure 9-8 on
page 9-14 and Figure 9-9 on page 9-15).
NOTE
CCFx refers to 5 separate bits, one for each PCA module (CCF0, CCF1, CCF2,
CCF3, CCF4). CCAPMx refers to 5 separate registers, one for each PCA
module (CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4).
CCF3, CCF4). CCAPMx refers to 5 separate registers, one for each PCA
module (CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4).
6.4
SERIAL PORT INTERRUPT
Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register (see
Figure 10-2 on page 10-3). Neither flag is cleared by a hardware vector to the service routine. The
service routine resolves RI or TI interrupt generation and clears the serial port request flag. The
serial port interrupt is enabled by bit ES in the IE0 register (see Figure 6-2).
Figure 10-2 on page 10-3). Neither flag is cleared by a hardware vector to the service routine. The
service routine resolves RI or TI interrupt generation and clears the serial port request flag. The
serial port interrupt is enabled by bit ES in the IE0 register (see Figure 6-2).
6.5
INTERRUPT ENABLE
Each interrupt source (with the exception of TRAP) may be individually enabled or disabled by
the appropriate interrupt enable bit in the IE0 register at S:A8H (see Figure 6-2). Note IE0 also
contains a global disable bit (EA). If EA is set, interrupts are individually enabled or disabled by
bits in IE0. If EA is clear, all interrupts are disabled.
the appropriate interrupt enable bit in the IE0 register at S:A8H (see Figure 6-2). Note IE0 also
contains a global disable bit (EA). If EA is set, interrupts are individually enabled or disabled by
bits in IE0. If EA is clear, all interrupts are disabled.