Cypress CY62158E 사용자 설명서
CY62158E MoBL
®
Document #: 38-05684 Rev. *D
Page 5 of 10
Switching Characteristics
Over the Operating Range
Parameter
Description
45 ns
Unit
Min
Max
Read Cycle
t
RC
Read Cycle Time
45
ns
t
AA
Address to Data Valid
45
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
45
ns
t
DOE
OE LOW to Data Valid
22
ns
t
LZOE
OE LOW to Low Z
5
ns
t
HZOE
OE HIGH to High Z
18
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
10
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High Z
18
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power Down
45
ns
Write Cycle
t
WC
Write Cycle Time
45
ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End
35
ns
t
AW
Address Setup to Write End
35
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
35
ns
t
SD
Data Setup to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
18
ns
t
LZWE
WE HIGH to Low Z
10
ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
10. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
11. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and any of these signals
can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.