Intel 253668-032US 사용자 설명서
Vol. 3 14-3
POWER AND THERMAL MANAGEMENT
•
IA32_APERF MSR (0xE8) increments in proportion to actual performance, while
accounting for hardware coordination of P-state and TM1/TM2; or software
initiated throttling.
accounting for hardware coordination of P-state and TM1/TM2; or software
initiated throttling.
•
The MSRs are per logical processor; they measure performance only when the
targeted processor is in the C0 state.
targeted processor is in the C0 state.
•
Only the IA32_APERF/IA32_MPERF ratio is architecturally defined; software
should not attach meaning to the content of the individual of IA32_APERF or
IA32_MPERF MSRs.
should not attach meaning to the content of the individual of IA32_APERF or
IA32_MPERF MSRs.
•
When either MSR overflows, both MSRs are reset to zero and continue to
increment.
increment.
•
Both MSRs are full 64-bits counters. Each MSR can be written to independently.
However, software should follow the guidelines illustrated in Example 14-1.
However, software should follow the guidelines illustrated in Example 14-1.
If P-states are exposed by the BIOS as hardware coordinated, software is expected
to confirm processor support for P-state hardware coordination feedback and use the
feedback mechanism to make P-state decisions. The OSPM is expected to either save
away the current MSR values (for determination of the delta of the counter ratio at a
later time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at
the start of the time window used for making the P-state decision. When not reset-
ting the values, overflow of the MSRs can be detected by checking whether the new
values read are less than the previously saved values.
Example 14-1 demonstrates steps for using the hardware feedback mechanism
provided by IA32_APERF MSR and IA32_MPERF MSR to determine a target P-state.
to confirm processor support for P-state hardware coordination feedback and use the
feedback mechanism to make P-state decisions. The OSPM is expected to either save
away the current MSR values (for determination of the delta of the counter ratio at a
later time) or reset both MSRs (execute WRMSR with 0 to these MSRs individually) at
the start of the time window used for making the P-state decision. When not reset-
ting the values, overflow of the MSRs can be detected by checking whether the new
values read are less than the previously saved values.
Example 14-1 demonstrates steps for using the hardware feedback mechanism
provided by IA32_APERF MSR and IA32_MPERF MSR to determine a target P-state.
Example 14-1. Determine Target P-state From Hardware Coordinated Feedback
DWORD PercentBusy; // Percentage of processor time not idle.
// Measure “PercentBusy“ during previous sampling window.
// Typically, “PercentBusy“ is measure over a time scale suitable for
// power management decisions
//
// RDMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between
// the two RDMSRs (for example, interrupts).
MCNT = RDMSR(IA32_MPERF);
ACNT = RDMSR(IA32_APERF);
// Typically, “PercentBusy“ is measure over a time scale suitable for
// power management decisions
//
// RDMSR of MCNT and ACNT should be performed without delay.
// Software needs to exercise care to avoid delays between
// the two RDMSRs (for example, interrupts).
MCNT = RDMSR(IA32_MPERF);
ACNT = RDMSR(IA32_APERF);
// PercentPerformance indicates the percentage of the processor
// that is in use. The calculation is based on the PercentBusy,
// that is the percentage of processor time not idle and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.
// Note that both values need to be calculated over the same
// time window.
// that is in use. The calculation is based on the PercentBusy,
// that is the percentage of processor time not idle and the P-state
// hardware coordinated feedback using the ACNT/MCNT ratio.
// Note that both values need to be calculated over the same
// time window.
PercentPerformance = PercentBusy * (ACNT/MCNT);