Texas Instruments TMS320DM355 사용자 설명서
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PRODUCT PREVIEW
5.14.1
ASP Electrical Data/Timing
TMS320DM355
Digital Media System-on-Chip (DMSoC)
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
5.14.1.1
Audio Serial Port (ASP) Timing
Table 5-35. Timing Requirements for ASP
(1)
(see
DM355
NO.
UNIT
MIN
MAX
15
tc(CLK)
Cycle time, CLK
CLK ext
38.5 or 2P
(2) (3)
ns
16
OTG(CLKS)
Pulse duration, CLKR/X high or CLKR/X low
CLKS ext
19.25 or P
(2) (3) (4)
ns
CLKR int
21
5
t
su(FRH-CKRL)
Setup time, external FSR high before CLKR low
ns
CLKR ext
6
CLKR int
0
6
t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low
ns
CLKR ext
6
CLKR int
21
7
t
su(DRV-CKRL)
Setup time, DR valid before CLKR low
ns
CLKR ext
6
CLKR int
0
8
t
h(CKRL-DRV)
Hold time, DR valid after CLKR low
ns
CLKR ext
6
CLKX int
21
10
t
su(FXH-CKXL)
Setup time, external FSX high before CLKX low
ns
CLKX ext
6
CLKX int
0
11
t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low
ns
CLKX ext
10
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
inverted.
(2)
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see
) .
(3)
Use which ever value is greater.
(4)
The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
Peripheral Information and Electrical Specifications
138