Fujitsu MHD2021AT 사용자 설명서
Interface
5-76
C141-E050-02EN
f)
When the command execution is completed, the device clears both BSY and
DRQ bits and asserts the INTRQ signal. Then, the host reads the Status
register.
DRQ bits and asserts the INTRQ signal. Then, the host reads the Status
register.
g)
The host resets the DMA channel.
Figure 5.7 shows the correct DMA data transfer protocol.
Figure 5.7 Normal DMA data transfer
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