Renesas R5S72647 사용자 설명서
![Renesas](https://files.manualsbrain.com/attachments/59153266feca598c11e08bf1f143ccfcf45441a4/common/fit/150/50/d3d06de51d338eb4f916b44a9629f9d48697a59cd7344be40cf24bae01c5/brand_logo.gif)
Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00
Page 2031 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Item Symbol Min.
Max.
Unit
Figure
FRE high pulse width
t
NSPH
0.5
t
wfcyc
5 ns
Figure
37.62
Read data setup time
t
NRDS
16
ns
Figures
37.62,
37.64
Read data hold time
t
NRDH
5
ns
Figures
37.62,
37.64
Data write setup time
t
NDWS
32
t
pcyc
ns
Figure
37.63
Command to status read transition
time
time
t
NCDSR
4
t
fcyc
ns
Figure
37.64
Command output off to status read
transition time
transition time
t
NCDFSR
3.5
t
fcyc
ns
Status read setup time
t
NSTS
2.5
t
fcyc
ns
FCE output setup time
t
NCES
8
t
pcyc
ns
Figure
37.60
FCE output hold time
t
NCEH
t
pcyc
ns
Figure
37.63
FCE output access time
t
NCEA
6
t
pcyc
ns
Figure
37.62
FCE output high-level hold time
t
NCEOH
2
t
pcyc
ns
Note: t
fcyc
indicates the period of one cycle of the FLCTL clock.
t
wfcyc
indicates the period of one cycle of the FLCTL clock when the value of the NANDWF bit
is 0. On the other hand, t
wfcyc
indicates the period of two cycles of the FLCTL clock when the
value of the NANDWF bit is 1.
t
pcyc
indicates the period of one cycle of the peripheral clock (P
).