Intel Xeon X3450 BX80605X3450 사용자 설명서

Intel® Xeon® Processor 3400 Series Datasheet, Volume 1

17

Processor

The 64-bit multi-core component (package)

Processor Core

The term “processor core” refers to Si die itself which can contain multiple 

execution cores. Each execution core has an instruction cache, data cache, and 

256-KB L2 cache. All execution cores share the L3 cache. 

Rank

A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These 

devices are usually, but not always, mounted on a single side of a DIMM.

SCI

System Control Interrupt. Used in ACPI protocol.

Storage Conditions

A non-operational state. The processor may be installed in a platform, in a tray, or 

loose. Processors may be sealed in packaging or exposed to free air. Under these 

conditions, processor landings should not be connected to any supply voltages, 

have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., 

unsealed packaging or a device removed from packaging material) the processor 

must be handled in accordance with moisture sensitivity labeling (MSL) as indicated 

on the packaging material.

TAC

Thermal Averaging Constant

TDP

Thermal Design Power

TOM

Top of Memory

TTM

Time-To-Market

V

CC

Processor core power rail

V

SS

Processor ground

V

TT

L3 shared cache, memory controller, and processor I/O power rail

V

DDQ

DDR3 power rail

VLD

Variable Length Decoding

x1

Refers to a Link or Port with one Physical Lane

x4

Refers to a Link or Port with four Physical Lanes

x8

Refers to a Link or Port with eight Physical Lanes

x16

Refers to a Link or Port with sixteen Physical Lanes