Intel D525 AU80610006225AA 사용자 설명서

44

Datasheet

•

Parameters not present for V

CC:

— No socket loadline slope - SKT_LL

— No socket loadline tolerance band 

— No maximum overshoot above VID (OS_AMP)

— No maximum overshoot time duration above VID (OS_TIME)

— No peak-to-peak ripple amplitude (RIPPLE)

— No thermal compensation voltage drift (THERMAL_DRIFT)

— No maximum DC test (current I_DC_MAX)

— No minimum DC test (current I_DC_MIN)

•

Parameters present for V

CC:

— Tolerance band (TOB) of ±50 mV

NOTES:
1.

Unless otherwise noted, all specifications in this table are based on estimates and 
simulations or empirical data. These specifications will be updated with characterized data 
from silicon measurements at a later date.

2.

Each processor is programmed with voltage identification value (VID), which is set at 
manufacturing and cannot be altered. Individual VID values are calibrated during 
manufacturing such that two processors at the same frequency may have different 
settings within the VID range. Please note this differs from the VID employed by the 
processor during a power management event.

3.

These are pre-silicon estimates and are subject to change.

VID

VID Range

0.8

1.175

V

V

CC

V

CC

 for processor core

See 

0.800 - 1.175

V

2,  3

V

CC,BOOT

Default V

CC 

voltage for initial 

power up

1.045

1.1

1.26

V

I

CC

I

CC

 for processor core 

Dual Core
Single Core

10.8

5.4

A

I

AH

I

CC 

Auto-Halt

Dual Core
Single Core

6.5

3.25

A

dI

CC/DT

V

CC 

power supply current slew rate 

at the processor pin package 
Dual Core
Single Core

5

2.5

A/µs