Intel 2 Duo T9300 EC80576GG0606M 사용자 설명서

18

Datasheet

Dynamic Cache Sizing allows the processor to flush and disable a programmable 

number of L2 cache ways upon each Deeper Sleep entry under the following 

conditions:

• The second core is already in C4 and Intel Enhanced Deeper Sleep state or C6 state 

is enabled (as specified in 

).

• The C0 timer that tracks continuous residency in the Normal package state has not 

expired. This timer is cleared during the first entry into Deeper Sleep to allow 

consecutive Deeper Sleep entries to shrink the L2 cache as needed. 

• The FSB speed to processor core speed ratio is below the predefined L2 shrink 

threshold. 

If the FSB speed-to-processor core speed ratio is above the predefined L2 shrink 

threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio 

will not be taken into account for Dynamic Cache Sizing decisions.

Core 1

CC0

Core 0

dpslp

assert

dprstp

assert

slp

assert

stpclk

assert

State 
Save

Level 6 

I/O Read 

State 
Save

mwait C6
or Level 6 

I/O Read 

mwait C6
or Level 6 

I/O Read 

CC0

CC6

CC6

Package 

C6

L2 

Shrink

Core 0 

dprst  

deassert

Package 

C6

H/W 

Reset

State 

Restore

ucode 

reset

CC0

dpsl  

deassert

sl  

deassert

stpclk  

deassert

State 

Restore

CC0

Core 1 

ucode 

reset