Intel 220 LE80557RE009512 데이터 시트
제품 코드
LE80557RE009512
Datasheet
29
Electrical Specifications
NOTES:
1.
1.
Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
NOTE:
1.
1.
information.
3.8.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs for the processor to recognize the proper signal state.
See
for the DC specifications. See
for additional timing
requirements for entering and leaving the low power states.
Table 9.
Signal Characteristics
Signals with R
TT
Signals with No R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:0], GTLREF[1:0], TCK, TDI, TMS,
TRST#
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:0], GTLREF[1:0], TCK, TDI, TMS,
TRST#
Open Drain Signals
1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, FCx
BR0#, TDO, FCx
Table 10.
Signal Reference Voltages
GTLREF
V
CCP
/2
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
1
, SMI#, STPCLK#, TCK
1
,
TDI
1
, TMS
1
, TRST#
1