Intel AT80604004878AA 사용자 설명서

Intel® Xeon® Processor 7500 Datasheet, Volume 1

47

 

V

min 

(Absolute 

Undershoot)

Single-ended minimum voltage

-0.3

-

-

V

1, 10

VRB-Diff

Differential ringback voltage 

threshold

-100

100

mV

3, 11

T

Stable

Allowed time before ringback

500

ps

3, 11

1. Measurement taken from single ended waveform.

2. Rise and Fall times are measured single ended between 245 mV and 455 mV of the clock swing.

3. Measurement taken from differential waveform.

4. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFLCLK-). The signal must be

monotic through the measurement region for rise and fall time. The 300 mV measurement window is centred on the differential

zero crossing. See 

.

5. Measured at crossing point where the instantaneous voltage value of the rising edge REFCLK+ equals the falling edge REFCLK-.

See 

6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all

crossing points for this measurement. See 

7. VHavg is the statistical average of the VH measured by the oscilloscope. The purpose of defining relative crossing point voltages

is to prevent a 250 mV Vcross with a 850 mV VH. Also this prevents the case of a 550 mV Vcross with a 660 mV VH. See

8. Defined as the total variation of all crossing voltages of Rising REFCLK+ and falling REFCLK-. This is the maximum allowed

variance in Vcross for any particular system. See 

9. Defined as the maximum instantaneous voltage including overshoot. See 

.

10.Defined as the minimum instantaneous voltage including undershoot. See 

11.TStable is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before

it is allowed to droop back into the VRB ±100 mV range. See 

.

Asynchronous GTL input pulse width

8

SYSCLKs

ERROR[0]_N, ERROR[1]_N, THERMTRIP_N, PROCHOT_N Output Edge 

Rate

0.7

2.3

V/ns

1

,

3

1.

These values are based on driving a 50Ω

 

transmission line into a 50Ω pullup.

ERROR[0]_N pulse width

16

16

b-clocks

MEM_THROTTLE0_N, MEM_THROTTLE1_N, LT-SX, RUNBIST, Input 

Edge Rate

0.5

V/ns

FORCE_PR_N pulse width

500

µs

PROCHOT_N pulse width

500

µs

PWRGOOD rise time

20

ns

PWRGOOD, RESET_N, FORCE_PR_N, ERROR[0]_N, ERROR[1]_N, 

SKTDIS_N Input Edge Rates

0.1

V/ns

2

,

3

,

4

2.

Deterministic reset.

RESET_N hold time w.r.t SYSCLK/SYSCLK_N

0.5

ns

5

RESET_N pulse width while PWRGOOD is active

1

ms

SYSCLK stable to PWRGOOD assertion

10

SYSCLK

THERMTRIP_N assertion until Vcc, and VCCCACHE removal

500

ms

Vcc

 

stable to PWRGOOD assertion

0.05

500

ms

V

REG

 stable to PWRGOOD assertion

1

ms

V

IO

 stable to VIOPWRGOOD assertion

1

500

ms

VIOPWRGOOD de-assertion to V

io

 outside specification

100

ns

VIOPWRGOOD rise time

20

ns

PWRGOOD assertion to RESET_N de-assertion

34

ms