Intel Xeon L3406 CM80616005010AA 사용자 설명서
제품 코드
CM80616005010AA
Datasheet, Volume 2
163
Processor Integrated I/O (IIO) Configuration Registers
3.6.1.2
TXT.ESTS—Intel
®
TXT Error Status Register
This register is used to read the status associated with various errors that might be
detected.
detected.
General Behavioral Rules:
• This register is available for read-only access from the Public configuration space.
• This register is available for read and write access from the Private configuration
• This register is available for read and write access from the Private configuration
space. Each status bit is cleared by writing to this register with a 1 in the
corresponding bit position.
corresponding bit position.
• The bits in this register are cleared by writing a 1 to the corresponding bit
positions. These bits are not cleared by a standard system reset.
Base: TXT_TXT Offset: 0008h
Base: TXT_PR Offset: 0008h
Base: TXT_PB_noWROffset: 0008h
Bit
Attr
Default
Description
7
RV
0
Reserved
6
RW1C
0
TXT.WAKE-ERROR.STS
The chipset sets this bit when it detects that there might have been secrets
The chipset sets this bit when it detects that there might have been secrets
in memory and a reset or power failure occurred.If this bit is set after a
system reset, the chipset will prevent memory accesses until specifically
enabled. The software that is authorized to enable the memory accesses
will also be responsible for clearing the secrets from memory.Software can
read chipset-specific registers to determine the specific cause of the error.
The location of those bits is beyond the scope of this specification. On a
reset, if NOP_ACK_WITH_SECRETS is received, then this bit is set to 1. On
a reset, if NOP_ACK_WITHOUT_SECRETS is received, then this bit is
cleared to 0.
This bit must be cleared if a read to FED4_0000h returns a 1 in Bit 0.
This bit must be cleared if a read to FED4_0000h returns a 1 in Bit 0.
5
RWC
0
TXT.ALIAS.FAULT
Set when the platform determines there is an address alias error that could
Set when the platform determines there is an address alias error that could
be a security violation. Software can clear this bit by writing a 1 to it.
4
RWC
0
Reserved.
This bit is set when the processor issues a write to TXT.ESTS.SET register
This bit is set when the processor issues a write to TXT.ESTS.SET register
with bit [4] = 1.
3
RWC
0
Reserved.
This bit is set when the processor issues a write to TXT.ESTS.SET register
This bit is set when the processor issues a write to TXT.ESTS.SET register
with bit [3] = 1.
2
RWC
0
TXT.MEMORY.ATTACK
This bit is set when there is some illegal read of DRAM. This bit is set when
This bit is set when there is some illegal read of DRAM. This bit is set when
the processor issues a write to TXT.ESTS.SET register with bit [2]=1.
Software can clear this bit by writing a 1 to it.
Software can clear this bit by writing a 1 to it.
1
RW1C
0
TXT.ROGUE.STS
The chipset sets this bit to indicate that some thread has left the secure
The chipset sets this bit to indicate that some thread has left the secure
environment improperly.
0
ROS
0
TXT.POISON Cycle Received
The chipset sets this bit to indicate that the TXT.POISON cycle has been
The chipset sets this bit to indicate that the TXT.POISON cycle has been
received. Note that this bit is sticky and is only cleared by a power cycle.
The effect of TXT.POISON is also held active through reset and so the
chipset is poisoned even after the reset. The only way to clear the poison
effect is to do a power cycle.