Intel Xeon L3406 CM80616005010AA 사용자 설명서
제품 코드
CM80616005010AA
System Address Map
290
Datasheet, Volume 2
5.5.2
SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are
unpredictable and may cause the system to hang:
unpredictable and may cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space
2. High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI Interface, and
PCI Express, and graphics devices). This is a BIOS responsibility.
PCI Express, and graphics devices). This is a BIOS responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
5. Any address translated through the GMADR TLB must not target DRAM from
A_0000h–F_FFFFh.
5.5.3
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM
space is effectively disabled. Processor originated accesses to the Compatible SMM
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise
they are forwarded to the DMI Interface. PCI Express and DMI Interface originated
accesses are never allowed to access SMM space.
space is effectively disabled. Processor originated accesses to the Compatible SMM
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise
they are forwarded to the DMI Interface. PCI Express and DMI Interface originated
accesses are never allowed to access SMM space.
Table 5-2.
SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible (C)
Range
High (H)
Range
TSEG (T)
Range
0
X
X
Disable
Disable
Disable
1
0
0
Enable
Disable
Disable
1
0
1
Enable
Disable
Enable
1
1
0
Disabled
Enable
Disable
1
1
1
Disabled
Enable
Enable