Intel Xeon L3406 CM80616005010AA 사용자 설명서
제품 코드
CM80616005010AA
System Address Map
294
Datasheet, Volume 2
bit. There is no decode enable bit for configuration cycle decoding towards either a
PCIe port or the internal CSR configuration space of IIO.
PCIe port or the internal CSR configuration space of IIO.
• The target decoding for internal VTdCSR space is based on whether the incoming
CSR address is within the VTdCSR range (limit is 8K plus the base, VTBAR).
• Each PCIe/DMI port in IIO has one special address range - I/OxAPIC
• No loopback supported, that is, a transaction originating from a port is never sent
• No loopback supported, that is, a transaction originating from a port is never sent
back to the same port and the decode ranges of originating port are ignored in
address decode calculations
address decode calculations
5.8.1.2
FWH Decoding
This section talks about how IIO allows for access to flash memory that is resident
below the IIO.
below the IIO.
• FWH accesses using an IIO are allowed only from Intel QuickPath Interconnect. No
accesses from JTAG/PCIe
• IIO indicates presence of bootable FWH to processor if it is with a FWH that
contains the boot code below the legacy PCH connected to it
• All FWH addresses (4 GB:4 GB–16 MB) and (1 MB:1 MB – 128 K) that do not
positively decode to IIO’s PCIe ports, are subtractively forwarded to its legacy
decode port.
decode port.
• When IIO receives a transaction from Intel QuickPath Interconnect within 4 GB:4
GB–16 MB or 1 MB:1 MB–128 K and there is no positive decode hit against any of
the other valid targets (if there is a positive decode hit to any of the other valid
targets, the transaction is sent to that target), then the transaction is forwarded to
DMI.
the other valid targets (if there is a positive decode hit to any of the other valid
targets, the transaction is sent to that target), then the transaction is forwarded to
DMI.
5.8.1.3
Other Outbound Target Decoding
• Other address ranges (besides CSR, FWH, I/OxAPIC) that need to be decoded per
PCIe/DMI port include the standard peer-to-peer bridge decode ranges (MMIOL,
MMIOH, I/O, VGA, CONFIG). Refer to PCI-PCI Bridge 1.2 Specification and PCI
Express Base Specification for details. These ranges are also summarized in
MMIOH, I/O, VGA, CONFIG). Refer to PCI-PCI Bridge 1.2 Specification and PCI
Express Base Specification for details. These ranges are also summarized in
.
• VTCSR
— Remote peer-to-peer accesses from Intel QuickPath Interconnect that target
VTCSR region are not completer aborted by IIO. If inbound protection is
needed, VTd translation table should be used to protect at the source IIO. If
the VTd table is not enabled, a Generic Protected Memory Range could be used
to protect. A last defense is to turn off IB peer-to-peer MMIO The remote peer-
to-peer support is an issue not yet closed completely yet.
— Remote peer-to-peer PCI configuration transactions from Intel QuickPath
Interconnect that target the internal bus number of IIO (regardless of device
number) are aborted by IIO.