Intel LF80550KF0804M 데이터 시트
Electrical Specifications
26
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Notes:
1.
Refer to
for signal descriptions.
Notes:
1.
Signals not included in the “Signals with R
TT
” list require termination on the baseboard. Please refer to
for the corresponding DC specifications.
2.
The BOOT_SELECT pin is not terminated to R
TT
. It has a 500-5000 Ω internal pullup.
The ODTEN signals enables or disables R
TT
. Those signals affected by ODTEN still
present R
TT
termination to the signal’s pin when the processor is placed in tri-state
mode.
Furthermore, the following signals are not affected when the processor is placed in tri-
state mode: BSEL[1:0], CVID[3:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], and
VTTEN.
state mode: BSEL[1:0], CVID[3:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], and
VTTEN.
Notes:
1.
These signals also have hysteresis added to the reference voltage. See
for more information.
2.7
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
The Dual-Core Intel® Xeon® Processor 7100 Series processor does not utilize CMOS
voltage levels on any signals that connect to the processor silicon. As a result, inputs
signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
and STPCLK# utilize GTL buffers. Legacy output THERMTRIP# utilizes a GTL+ output
buffer. All of these asynchronous signals follow the same DC requirements as GTL+
signals; however, the outputs are not driven high (during the logical 0-to-1 transition)
by the processor. FERR#/PBE#, IERR#, and PROCHOT# have now been defined as
AGTL+ asynchronous signals as they include an active pMOS device. GTL+
asynchronous and AGTL+ asynchronous signals do not have setup or hold time
specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six
BCLKs in order for the processor to recognize the proper signal state, except during
power-on configuration. See
voltage levels on any signals that connect to the processor silicon. As a result, inputs
signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
and STPCLK# utilize GTL buffers. Legacy output THERMTRIP# utilizes a GTL+ output
buffer. All of these asynchronous signals follow the same DC requirements as GTL+
signals; however, the outputs are not driven high (during the logical 0-to-1 transition)
by the processor. FERR#/PBE#, IERR#, and PROCHOT# have now been defined as
AGTL+ asynchronous signals as they include an active pMOS device. GTL+
asynchronous and AGTL+ asynchronous signals do not have setup or hold time
specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six
BCLKs in order for the processor to recognize the proper signal state, except during
power-on configuration. See
for the DC specifications for the GTL+
asynchronous and AGTL+ asynchronous signal groups.
Table 2-7.
Signal Description Table
Signals with R
TT
1
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT
2
, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DEP[7:0]#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, ID[7:0]#,
IDS#, LOCK#, MCERR#, OOD#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Signals with R
L
BINIT#, BNR#, HIT#, HITM#, MCERR#
Table 2-8.
Signal Reference Voltages
GTLREF
V
TT
/ 2
A20M#, A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DEP[7:0]#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
FORCEPR#, HIT#, HITM#, ID[7:0]#, IDS#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LOCK#,
MCERR#, ODTEN, OOD#, REQ[4:0]#, RESET#,
RS[2:0]#, RSP#, SMI#, STPCLK#, TRDY#
BOOT_SELECT, PWRGOOD
1
, TCK
1
, TDI
1
, TMS
1
,
TRST#
1
, VIDPWRGD