Intel 2 Duo T7700 LE80537GG0564M 사용자 설명서

Datasheet

17

Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# 

deassertion when either core requests a core state other than C4 or either core 

requests a processor performance state other than the lowest operating point. 

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power-

saving capabilities by allowing the processor to further reduce core voltage once the L2 

cache has been reduced to zero ways and completely shut down. The following events 

occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 causes the package to issue a P_LVL4 IO Read. 
• Every concurrent package C4 entry reduces the L2 Cache a certain number of 

cache ways, after which another P_LVL4 IO Read is issued to the chipset. By 

default, half the cache is flushed per concurrent C4 entry. 

• Once the cache is flushed, P_LVL4 IO Reads continue to be issued. 
• The processor drives the VID code corresponding to the Intel Enhanced Deeper 

Sleep state core voltage on the VID[6:0] pins. 

At this point, snoops to the L2 are still serviced, which reduces the amount of time the 

processor can reside at the Intel Enhanced Deeper Sleep state core voltage. 

To improve the Intel Enhanced Deeper Sleep state residency, the (G)MCH features 

P_LVL5 IO Read support. When enabled, the CPU issues a P_LVL5 IO read, once the L2 

cache is flushed. The P_LVL5 IO read triggers a special chipset sequence to notify the 

chipset to redirect all FSB traffic, except APIC messages, to memory instead of L2 

cache. Therefore, the processor remains at the Intel Enhanced Deeper Sleep state core 

voltage for a longer period of time.

Dynamic Cache Sizing allows the processor to flush and disable a programmable 

number of L2 cache ways upon each Deeper Sleep entry under the following 

conditions:

• The second core is already in C4 and the Intel Enhanced Deeper Sleep state is 

enabled (as specified in 

).

• The C0 timer, which tracks continuous residency in the Normal package state, has 

not expired. This timer is cleared during the first entry into Deeper Sleep to allow 

consecutive Deeper Sleep entries to shrink the L2 cache as needed. 

• The FSB speed to processor core speed ratio is below the predefined L2 shrink 

threshold. 

If the FSB speed to processor core speed ratio is above the predefined L2 shrink 

threshold, then L2 cache expansion is requested. If the ratio is zero, then the ratio is 

not taken into account for Dynamic Cache Sizing decisions.

Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state 

expands the L2 cache to two ways and invalidate previously disabled cache ways. If the 

L2 cache reduction conditions stated above still exist when the last core returns to C4 

and the package enters Intel Enhanced Deeper Sleep state, then the L2 is shrunk to 

zero again. If a core requests a processor performance state resulting in a higher ratio 

than the predefined L2 shrink threshold, the C0 timer expires, or the second core (not 

the one currently entering the interrupt routine) requests the C1, C2, or C3 states, 

then all of L2 expands upon the next interrupt event.

L2 cache shrink prevention may be enabled as needed on occasion through an 

MWAIT(C4) sub-state field. If shrink prevention is enabled the processor does not enter 

Intel Enhanced Deeper Sleep state because the L2 cache remains valid and in full size.