Aopen mx3l 사용자 설명서
Hardware Installation
2-17
The following table lists the recommended DRAM combinations of DIMM:
DIMM
Data chip
Data chip
Bit size
per side
per side
Single/
Double side
Double side
Chip
count
count
DIMM size
Recommended
1M by 16
1Mx64
x1
4
8MB
Yes
1M by 16
1Mx64
x2
8
16MB
Yes
2M by 8
2Mx64
x1
8
16MB
Yes
2M by 8
2Mx64
x2
16
32MB
Yes
4M by 16
4Mx64
x1
4
32MB
Yes
4M by 16
4Mx64
x2
8
64MB
Yes
8M by 8
8Mx64
x1
8
64MB
Yes
8M by 8
8Mx64
x2
16
128MB
Yes
DIMM
Data chip
Data chip
Bit size
per side
per side
Single/
Double side
Double side
Chip
count
count
DIMM size
Recommended
2M by 32
2Mx64
x1
2
16MB
Yes, but not tested.
2M by 32
2Mx64
x2
4
32MB
Yes, but not tested.
The following table lists the possible DRAM combinations that is NOT
recommended:
recommended:
DIMM
Data chip
Data chip
Bit size
per side
per side
Single/
Double side
Double side
Chip
count
count
DIMM
size
size
Recommended
4M by 4
4Mx64
x1
16
32MB
No
4M by 4
4Mx64
x2
32
64MB
No
16M by 4
16Mx64
x1
16
128MB
No
16M by 4
16Mx64
x2
32
256MB
No
Tip: The parity mode uses 1 parity bit for each byte, normally
it is even parity mode, that is, each time the memory data is
updated, parity bit will be adjusted to have even count "1" for
each byte. When next time, if memory is read with odd
number of "1", the parity error is occurred and this is called
single bit error detection.
it is even parity mode, that is, each time the memory data is
updated, parity bit will be adjusted to have even count "1" for
each byte. When next time, if memory is read with odd
number of "1", the parity error is occurred and this is called
single bit error detection.