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RH-3
System Module
CCS Technical Documentation
Page 28
 Nokia Corporation        Confidential
Issue 1 06/2003
sition times). The VCTCXO output is AC, coupled to Yoda, Jedi, UHF PLL, and the digital 
ASICs (see the following figure) to eliminate DC incompatibility between those pins.
Figure 13: VCTCXO clock distribution
Receiver
Figure 14: RH-3 Receiver block diagram
The receiver is a dual conversion I/Q receiver with a first IF of 183.6 MHz. The front-end 
RFIC (Alfred) contains a low noise amplifier (LNA), a radio frequency amplifier (RFA), a 
down-converter, an intermediate frequency amplifier (IFA), and a local oscillator ampli-
fier (LOA). Between the LNA and the RFA is a bandpass filter which will reject out-of-
band spurious and act as image rejection. The IF filter is between the Alfred IC and the 
BatmanD IC. The purpose of this filter is to guarantee rejection in adjacent and alternate 
channels.