National Instruments DIO 6533 사용자 설명서

Chapter 5

Signal Timing

DIO 6533 User Manual

5-30

© National Instruments Corporation

Figure 5-26.  Burst Mode Output Timing (Default)

t

pc

PCLK cycle time

50

—

t

pw

PCLK high pulse duration

20

—

t

pl

PCLK low pulse duration

20

—

t

rs

Setup time from REQ valid to PCLK falling 
edge

1

—

t

rh

Hold time from PCLK to REQ invalid

0

—

t

pa

PCLK to ACK valid

—

22

t

ah

Hold time from PCLK to ACK invalid

3

—

t

pdo

PCLK to output data valid

—

28

t

doh

Hold time from PCLK to output data invalid

5

—

All timing values are in nanoseconds.

PCLK

ACK

Data Out

REQ

trs

tpa

tpdo

tpw

tpl

tpc

tdoh

trh

tah