IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
Exceptions
Page 158 of 377
gx_04.fm.(1.2)
March 27, 2006
4.3.3 Machine State Register (MSR)
Reserved
POW
Res
e
rv
ed
ILE EE PR FP ME
FE
0
SE BE
FE
1
Res
e
rv
ed
IP IR DR
Res
e
rv
ed
PM RI LE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bits
Field Name
Description
0:12
Reserved
Reserved
1
Bits
Description
0
Full function
1:4
Partial function
5:9
Full function
10:12
Partial function
13
POW
Power management enable
0
0
Power management disabled (normal operation mode).
1
Power management enabled (reduced power mode).
Power management functions are implementation-dependent. See Chapter 10, Power
and Thermal Management, on page 335.
and Thermal Management, on page 335.
14
Reserved
Reserved. Implementation-specific
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE]
to select the endian mode for the context established by the exception.
to select the endian mode for the context established by the exception.
16
EE
External interrupt enable
0
0
The processor delays recognition of external interrupts and decrementer excep-
tion conditions.
tion conditions.
1
The processor is enabled to take an external interrupt or the decrementer excep-
tion.
tion.
17
PR
Privilege level
0
The processor can execute both user- and supervisor-level instructions.
1
The processor can only execute user-level instructions.
18
FP
Floating-point available
0
The processor prevents dispatch of floating-point instructions, including floating-
point loads, stores, and moves.
point loads, stores, and moves.
1
The processor can execute floating-point instructions and can take floating-point
enabled program exceptions.
enabled program exceptions.
19
ME
Machine check enable
0
0
Machine-check exceptions are disabled. If one occurs, the system enters a
checkstop.
checkstop.
1
Machine-check exceptions are enabled.
20
FE0
IEEE floating-point exception mode 0 (see Table 4-4 on page 160).
21
SE
Single-step trace enable
0
0
The processor executes instructions normally.
1
The processor generates a single-step trace exception upon the successful exe-
cution of every instruction except rfi, isync, and sc. Successful execution means
that the instruction caused no other exception.
cution of every instruction except rfi, isync, and sc. Successful execution means
that the instruction caused no other exception.
1. Full function reserved bits are saved in SRR1 when an exception occurs; they are saved in the same bit locations in SRR1 that
they occupy in MSR. Partial function reserved bits are not saved.