IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
gx_04.fm.(1.2)
March 27, 2006
March 27, 2006
Exceptions
Page 169 of 377
When a machine-check exception is taken, instruction fetching resumes at offset 0x00200 from the physical
base address indicated by MSR[IP].
base address indicated by MSR[IP].
4.5.2.2 Checkstop State (MSR[ME] = 0)
If MSR[ME] = 0 and a machine check occurs, the processor enters the checkstop state. The 750GX
processor can also be forced into the checkstop state by the assertion of checkstop input (CKSTP_IN), the
primary input signal.
processor can also be forced into the checkstop state by the assertion of checkstop input (CKSTP_IN), the
primary input signal.
When a processor is in checkstop state, instruction processing is suspended and generally cannot resume
without the processor being reset. The contents of all latches are frozen within two cycles upon entering
checkstop state.
without the processor being reset. The contents of all latches are frozen within two cycles upon entering
checkstop state.
4.5.3 DSI Exception (0x00300)
A DSI exception occurs when no higher-priority exception exists and an error condition related to a data
memory access occurs. The DSI exception is implemented as it is defined in the PowerPC Architecture
(OEA). In case of a TLB miss for a load, store, or cache operation, a DSI exception is taken if the resulting
hardware table search causes a page fault.
memory access occurs. The DSI exception is implemented as it is defined in the PowerPC Architecture
(OEA). In case of a TLB miss for a load, store, or cache operation, a DSI exception is taken if the resulting
hardware table search causes a page fault.
On the 750GX, a DSI exception is taken when a load or store is attempted to a direct-store segment
(SR[T] = 1). In the 750GX, a floating-point load or store to a direct-store segment causes a DSI exception
rather than an alignment exception, as specified by the PowerPC Architecture.
(SR[T] = 1). In the 750GX, a floating-point load or store to a direct-store segment causes a DSI exception
rather than an alignment exception, as specified by the PowerPC Architecture.
The 750GX also implements the data address breakpoint facility, which is defined as optional in the PowerPC
Architecture and is supported by the optional Data Address Breakpoint Register (DABR). Although the archi-
tecture does not strictly prescribe how this facility must be implemented, the 750GX follows the recommenda-
tions provided by the architecture and described in the Chapter 2, “Programming Model” and Chapter 6,
“Exceptions” in the PowerPC Microprocessor Family: The Programming Environments Manual.
Architecture and is supported by the optional Data Address Breakpoint Register (DABR). Although the archi-
tecture does not strictly prescribe how this facility must be implemented, the 750GX follows the recommenda-
tions provided by the architecture and described in the Chapter 2, “Programming Model” and Chapter 6,
“Exceptions” in the PowerPC Microprocessor Family: The Programming Environments Manual.
4.5.4 ISI Exception (0x00400)
An ISI exception occurs when no higher-priority exception exists and an attempt to fetch the next instruction
fails. This exception is implemented as it is defined by the PowerPC Architecture (OEA), and is taken for the
following conditions:
fails. This exception is implemented as it is defined by the PowerPC Architecture (OEA), and is taken for the
following conditions:
• The effective address cannot be translated.
• The fetch access is to a no-execute segment (SR[N] = 1).
• The fetch access is to guarded storage and MSR[IR] = 1.
• The fetch access is to a segment for which SR[T] is set.
• The fetch access violates memory protection.
• The fetch access is to a no-execute segment (SR[N] = 1).
• The fetch access is to guarded storage and MSR[IR] = 1.
• The fetch access is to a segment for which SR[T] is set.
• The fetch access violates memory protection.
When an ISI exception is taken, instruction fetching resumes at offset 0x00400 from the physical base
address indicated by MSR[IP].
address indicated by MSR[IP].
4.5.5 External Interrupt Exception (0x00500)
An external interrupt is signaled to the processor by the assertion of the external interrupt signal (INT). The
INT signal is expected to remain asserted until the 750GX takes the external interrupt exception. If INT is
negated early, recognition of the interrupt request is not guaranteed. After the 750GX begins execution of the
external interrupt handler, the system can safely negate the INT. When the 750GX detects assertion of INT, it
INT signal is expected to remain asserted until the 750GX takes the external interrupt exception. If INT is
negated early, recognition of the interrupt request is not guaranteed. After the 750GX begins execution of the
external interrupt handler, the system can safely negate the INT. When the 750GX detects assertion of INT, it