IBM powerpc 750gx 사용자 설명서
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_11.fm.(1.2)
March 27, 2006
March 27, 2006
Performance Monitor and System Related Features
Page 363 of 377
11.10 750GX Parity
Parity is implemented for the following arrays: instruction cache, instruction tag, data cache, data tag, and
L2 tag. All parity errors, when parity is enabled, result in either a machine-check or checkstop interrupt that is
not recoverable.
L2 tag. All parity errors, when parity is enabled, result in either a machine-check or checkstop interrupt that is
not recoverable.
For all of the following arrays, parity for a given set of data is a one if there is an odd number of ones in the
data (even parity).
data (even parity).
Parity is computed each time data is written to the arrays, independent of the parity checking enable/disable
control bits.
control bits.
The Force Bad Parity control bits (5 bits) are provided as user visible bits in the HID2 control register and
control the parity bits written when the arrays are written. This is again independent of the parity
enable/disable control bits.
control the parity bits written when the arrays are written. This is again independent of the parity
enable/disable control bits.
The parity checking enable/disable control bits are provided to select when parity is to be checked for reads
by array group (L1 instruction cache and tag, L1 data cache and tag, and L2 tag). If parity checking is enabled
and bad parity is found on a read for the enabled array, then the MSR(ME) bit controls the action taken by the
processor for the parity error. Parity checking can be enabled or disabled at any time in the code stream
without changing the array enable/disable state, and the arrays do not require invalidation.
by array group (L1 instruction cache and tag, L1 data cache and tag, and L2 tag). If parity checking is enabled
and bad parity is found on a read for the enabled array, then the MSR(ME) bit controls the action taken by the
processor for the parity error. Parity checking can be enabled or disabled at any time in the code stream
without changing the array enable/disable state, and the arrays do not require invalidation.
The MSR(ME) bit enables the processor to take a machine-check interrupt allowing the operating system to
determine the failing array. If this bit is not asserted, then the processor will take a checkstop. See
Section 4.5.2.1, Machine-Check Exception Enabled (MSR[ME] = 1), on page 168 for further details.
determine the failing array. If this bit is not asserted, then the processor will take a checkstop. See
Section 4.5.2.1, Machine-Check Exception Enabled (MSR[ME] = 1), on page 168 for further details.
The parity status bits are set at the time of the detection of bad parity only when the array parity enable is set.
These bits are by array group (L1 instruction cache and tag, L2 data cache and tag, and L1 tag) and are
helpful for determining the problem within the machine-check interrupt handler.
These bits are by array group (L1 instruction cache and tag, L2 data cache and tag, and L1 tag) and are
helpful for determining the problem within the machine-check interrupt handler.
The HID2 Register updates are not serialized in the processor. Therefore, it is strongly recommended to
include an Instruction Synchronization (isync) instruction after any write to the HID2 Register to ensure the
changes are complete before proceeding in the code stream.
include an Instruction Synchronization (isync) instruction after any write to the HID2 Register to ensure the
changes are complete before proceeding in the code stream.