Intel architecture ia-32 사용자 설명서
Vol. 3A 17-39
IA-32 ARCHITECTURE COMPATIBILITY
bus to send the interrupt vector to the processor. After receiving the interrupt request signal, the
processor asserts LOCK# to insure that no other data appears on the data bus until the interrupt
vector is received. This bus locking does not occur on the P6 family processors.
processor asserts LOCK# to insure that no other data appears on the data bus until the interrupt
vector is received. This bus locking does not occur on the P6 family processors.
17.35. BUS HOLD
Unlike the 8086 and Intel 286 processors, but like the Intel386 and Intel486 processors, the P6
family and Pentium processors respond to requests for control of the bus from other potential
bus masters, such as DMA controllers, between transfers of parts of an unaligned operand, such
as two words which form a doubleword. Unlike the Intel386 processor, the P6 family, Pentium
and Intel486 processors respond to bus hold during reset initialization.
family and Pentium processors respond to requests for control of the bus from other potential
bus masters, such as DMA controllers, between transfers of parts of an unaligned operand, such
as two words which form a doubleword. Unlike the Intel386 processor, the P6 family, Pentium
and Intel486 processors respond to bus hold during reset initialization.
17.36. MODEL-SPECIFIC EXTENSIONS TO THE IA-32
Certain extensions to the IA-32 are specific to a processor or family of IA-32 processors and
may not be implemented or implemented in the same way in future processors. The following
sections describe these model-specific extensions. The CPUID instruction indicates the avail-
ability of some of the model-specific features.
may not be implemented or implemented in the same way in future processors. The following
sections describe these model-specific extensions. The CPUID instruction indicates the avail-
ability of some of the model-specific features.
17.36.1 Model-Specific Registers
The Pentium processor introduced a set of model-specific registers (MSRs) for use in control-
ling hardware functions and performance monitoring. To access these MSRs, two new instruc-
tions were added to the IA-32 architecture: read MSR (RDMSR) and write MSR (WRMSR).
The MSRs in the Pentium processor are not guaranteed to be duplicated or provided in the next
generation IA-32 processors.
ling hardware functions and performance monitoring. To access these MSRs, two new instruc-
tions were added to the IA-32 architecture: read MSR (RDMSR) and write MSR (WRMSR).
The MSRs in the Pentium processor are not guaranteed to be duplicated or provided in the next
generation IA-32 processors.
The P6 family processors greatly increased the number of MSRs available to software. See
Appendix B, “Model-Specific Registers (MSRs),” for a complete list of the available MSRs.
The new registers control the debug extensions, the performance counters, the machine-check
exception capability, the machine-check architecture, and the MTRRs. These registers are
accessible using the RDMSR and WRMSR instructions. Specific information on some of these
new MSRs is provided in the following sections. As with the Pentium processor MSR, the P6
family processor MSRs are not guaranteed to be duplicated or provided in the next generation
IA-32 processors.
Appendix B, “Model-Specific Registers (MSRs),” for a complete list of the available MSRs.
The new registers control the debug extensions, the performance counters, the machine-check
exception capability, the machine-check architecture, and the MTRRs. These registers are
accessible using the RDMSR and WRMSR instructions. Specific information on some of these
new MSRs is provided in the following sections. As with the Pentium processor MSR, the P6
family processor MSRs are not guaranteed to be duplicated or provided in the next generation
IA-32 processors.
17.36.2 RDMSR and WRMSR Instructions
The RDMSR (read model-specific register) and WRMSR (write model-specific register)
instructions recognize a much larger number of model-specific registers in the P6 family proces-
sors. (See “RDMSR—Read from Model Specific Register” and “WRMSR—Write to Model
Specific Register” in the IA-32 Intel® Architecture Software Developer’s Manual, Volumes
2A & 2B for more information.)
instructions recognize a much larger number of model-specific registers in the P6 family proces-
sors. (See “RDMSR—Read from Model Specific Register” and “WRMSR—Write to Model
Specific Register” in the IA-32 Intel® Architecture Software Developer’s Manual, Volumes
2A & 2B for more information.)