jetway 601cfr1c 사용자 설명서

 
 
 
                                                                                                                                                                                                                                                                                                                                                

 
 
 

 

 
 

The “Advanced DRAM Control” includes settings for the chipset dependents features.  
These features are related to system performance.  Make sure you fully understand the 
items contained in this menu before you try to change anything.  You may change the 
parameter settings to improve system performance.  However, it may cause your 
system to be unstable if the setting is not correct for your system configuration.  

↑↓→←:Move  Enter:Select  +/-/PU/PD:Value  F10:Save  ESC:Exit  F1:General Help

 
Precharge Command 
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before 
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.  Fast 
gives faster performance; and Slow gives more stable performance.  This field applies only 
when synchronous DRAM is installed in the system.  The settings are: 2 and 3. 
 
Active Command 
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when 
DRAM is written to, read from, or refreshed.  Fast gives faster performance; and Slow gives 
more stable performance.  This field applies only when synchronous DRAM is installed in the 
system.  The settings are: 2 and 3. 
Active to CMD Command 
Select the number of SCLKs for an access cycle.  The settings are: 5/7 and 6/8. 
 
SDRAM Cycle Length