jetway 603tcr1c 사용자 설명서

 
 
 
                                                                                                                                                                                                                                                                                                                                                         

 
 
 

 

↑↓→←

 
Precharge Command 
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before 
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.  Fast 
gives faster performance; and Slow gives more stable performance.  This field applies only 
when synchronous DRAM is installed in the system.  The settings are: 2 and 3. 
 
Active Command 
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used 
when DRAM is written to, read from, or refreshed.  Fast gives faster performance; and 
Slow gives more stable performance.  This field applies only when synchronous DRAM is 
installed in the system.  The settings are: 2 and 3. 
 
Active to CMD Command 
Select the number of SCLKs for an access cycle.  The settings are: 5/7 and 6/8. 
 
SDRAM Cycle Length 
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends 
on the DRAM timing.  The settings are: 2 and 3. 
PCI Delay Transaction 
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.  
Select Enabled to support compliance with PCI specification version 2.1.  The settings are: 
Enabled and Disabled.