jetway 603tcr4a 사용자 설명서
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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
Integrated Peripherals
Item Help
> OnChip IDE Function [Press Enter]
> OnChip DEVICE Function Press Enter
> OnChip SUPERIO Function Press Enter
Init Display First PCI Slot
> OnChip DEVICE Function Press Enter
> OnChip SUPERIO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑↓→←
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip DEVICE Function
Please refer to section 3-7-2
Please refer to section 3-7-2
OnChip SUPERIO Function
Please refer to section 3-7-3
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The
settings are: PCI Slot, AGP Slot.
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The
settings are: PCI Slot, AGP Slot.